As part of circuit design, electronic design automation (EDA) software systems commonly perform placement and routing to map the logic of a circuit design to a physical implementation of the circuit design. These processes can impact various aspects of the physical implementation including, without limitation, one or more of area usage, timing delays, and power consumption by included circuit components and data paths (e.g., nets) therebetween, all of which can impact actual performance of the physical circuit.
Clustering, which is typically a part of the placement process, can group or associate a plurality of circuit components (e.g., highly connected cells) into a clustered component, which in turn can be treated as a single component for placement and routing purposes. Clustering can determine the quality of circuit component placement (e.g., with respect to area usage, timing delays, or power consumption), can ensure that a physical implementation of a circuit design meets various design constraints (e.g., capacity, pin, or timing constraints), and can even determine the runtime of the placement process.